Here is a plot of my SR values against frequency.

The X axis is frequency.

The Y axis is calculated power. Power is calculated from P=C*F*V^2. Where P is power in Watts, C is capacitance in Farads, V^2 is volts squared measured in Volts.

The voltage is calculated by the base voltage plus the number of voltage steps(0.0125V per step). So step 20 is (0.0125V*20) +0.6V=0.85V

Unfortunately I have no idea what the gate capacitance of the chip is. I have set it as 0.1F which is INSANELY high, however it is just a multiplication factor so it simply scales the output of the equation. So the power values are total nonsense however the shape of the graph is what is important.





As you can see the voltage steps increase linearly, the power required increases exponentially. From this I would conclude that the 'most bang for buck' is in fact at 600MHz.

//EDIT: Real Conclusions

You can see from the graph that the difference in power use between 125-250MHz is negligible. When you consider the performance hit you take by activating 125MHz it makes sense to avoid it. Here doubling the frequency takes a tiny amount of power.

after 250MHz the increase in power use is almost linear up to 600MHz. Above 600 the power use line changes to a much higher gradient. This means increases in speed come at a much higher power cost.

meh, TBC.