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Posts: 2,152 | Thanked: 1,490 times | Joined on Jan 2006 @ Czech Republic
#531
Originally Posted by fanoush View Post
Thanks for testing. This means the code really does not work on many (all?) devices. Let's just hope it is my bug and can be fixed. It seems unlikely that someone inside Nokia bothered to write the tearsync code for N770 (which is completely different than code for n800) but the hardware in fact does not support it. Still it never made into official N770 kernel so maybe they found it later, who knows.
Reviving this one year old issue. Got tearsync support working with Nokia 770 :-)


Working source patch http://fanoush.wz.cz/maemo/#tearsync.
Works for me but take is as experimental code. I have tested it with two (=all?) widely available 770 board revisions - 1602 and 1802.

For kernel image get one of SDHC ones http://fanoush.wz.cz/maemo/#sdhc it is now part of them. If you already flashed one of them before, please redownload and reflash, previous versions had the non-working tearsync version included by mistake. It was harmless unless you actually try it with mplayer and use options below.

All source patches and kernel configuration used for compiling the image is now inside .tar.gz file in 'source' directory.

After flashing zImage from the archive, you can test it with mplayer arguments '-vo nokia770:tearsync=1'. If it works, you can also set it as default by adding line to /home/user/.mplayer/config
Code:
# Write your default config options here!
vo=nokia770:tearsync=1
Or to enable yuv420 mode too (gives slight speedup), you can add
Code:
# Write your default config options here!
vo=nokia770:tearsync=1,yuv420=1
So after approx. one year delay we finally have it working. What took so long? Basically it was just lack of information, magic words are "pin muxing, ball G20, register 4, value 6, offset 6". The original code posted year ago was OK, it was just a matter of enabling TE pin input on OMAP side. Sadly pin muxing is done in bootloader and 770 bootloader have this disabled. Also getting this information was a pain since TI pretends there is no such thing as SoSSI in OMAP1 chips, documentation for SoSSI was intentionally removed from current and some past revisions of OMAP5912 datasheets.
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Last edited by fanoush; 2008-04-08 at 07:03. Reason: links changed, now part of SDHC kernels
 

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