ARM926TEJ core subsystem

* Up to 220 MHz ARM926TEJ V5 architecture (maximum frequency)
* 32KB I-cache; 16KB D-cache
* Java acceleration
* Support for 32-bit and 16-bit (thumb mode) instruction sets
* Data and program MMUs
* Two 64-entry translation look-aside buffers (TLBs) for MMUs
* 17-word write buffer