Because that device is an eMMC block device, NOT a MTD device. Some years ago people realized it's a lot of fuss to work with MTD-s on the software level (wear leveling ? block management ? addressing ? error correction ? spare blocks ? MLC vs SLC ? CPU overhead ?), and put all this functionality, tailor made for that particular flash device, into something that is known as managed NAND (=aka eMMC). Take a look for some pretty pictures at http://download.micron.com/pdf/prese...nHEC_Cooke.pdf (talks about eMMC around page 55)