To precisely time small snippets of C code there is a need for a high-precision, low latency, wall clock timer. The x86 and most other architectures provides asm inlines to read the processor clock. With ARMv7 this should be possible with code like
However, attempting to use this with GCC asm inline on the N900 returns Illegal instruction. Is there any other mechanism to achieve this ?

Admittedly I know very little about ARMs, multitasking OSs, N900 specific programming or N900 hardware...

So just guessing/speculating: Might those be privileged (i.e. kernel level) instructions? Are you working on kernel level or user level? I can imagine there being some mechanism in the OS to signal HW timer based events to user level processes...

The real reason of me replying to your post (other than that of feeling the need to show off my complete lack of knowledge on the subject matter!) is an idea I got a while ago: I was pondering whether it might be possible to create a stable timer based quasi-VSYNC "service" on the N900 (supposedly lacking access to a real VSYNC interrupt source). If there's an accessible HW clock on the N900 whose frequency could be divided to exactly match the screen refresh rate, shouldn't it then be possible to create a calibratable (manually adjusting the periodic timer event phase once after every reboot) universal quasi-VSYNC service for all other applications to tap into?

Since you're already investigating the HW timers on the N900 I thought perhaps we could find the answers for all these questions together!

(Now if only I could get MADDE working on my machines. For some reason MADDE is causing some really heavy USB problems at both ends of the cable - after trying (and failing every time) to make a MADDE USB connection between my N900 and my WinXP PC I need to reboot BOTH machines before even PC Suite agrees to connect again!)

The hardware you are looking for is called a Performance Monitoring Unit (PMU) in ARM terminology. The PMU is found on Cortex v7A and v7R devices. You can access a cycle counter as well as three programmable event counters. I've used the module for bare metal benchmarking on a number of v7R devices (embedded safety systems).

I am not sure of GCC syntax, but I suspect the Cortex A8 TRM has an example of use which follows ARM RVCT syntax, as found in other Cortex TRMs. I believe you may also need to be in supervisor mode to access the PMU, which might be a problem.