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2009-11-25
, 21:01
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Posts: 37 |
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Joined on May 2009
@ Nicholasville, Kentucky, USA
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#322
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2009-11-25
, 21:06
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Posts: 388 |
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Joined on Oct 2009
@ London, UK
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#323
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2009-11-25
, 21:13
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Posts: 114 |
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Joined on Nov 2009
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#324
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The Following User Says Thank You to Megacrazy For This Useful Post: | ||
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2009-11-25
, 21:28
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Posts: 2,041 |
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Joined on Mar 2006
@ Houston
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#325
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2009-11-25
, 21:44
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Posts: 4,672 |
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Joined on Jul 2008
@ Springfield, MA, USA
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#326
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Hello Megacrazy,
Yes the scrolling is spotty in the RSS app. It used to be like this in the previous versions also.
But does it effect the use of the rss app significantly? I personally dont think so.I am quite okay with how it is. I think your expectations are very very high...
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2009-11-25
, 21:50
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Posts: 114 |
Thanked: 113 times |
Joined on Nov 2009
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#327
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Hello Megacrazy,
Yes the scrolling is spotty in the RSS app. It used to be like this in the previous versions also.
But does it effect the use of the rss app significantly? I personally dont think so.I am quite okay with how it is. I think your expectations are very very high...
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2009-11-25
, 21:57
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Posts: 2,041 |
Thanked: 1,066 times |
Joined on Mar 2006
@ Houston
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#328
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The Following 2 Users Say Thank You to sachin007 For This Useful Post: | ||
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2009-11-25
, 22:00
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Posts: 23 |
Thanked: 3 times |
Joined on Nov 2009
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#329
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2009-11-25
, 22:03
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Posts: 130 |
Thanked: 7 times |
Joined on Nov 2009
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#330
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N900 also has a lot larger resolution to move around than what is on the iPhone. I think the scrolling is really nice in the browser for example, any jerkiness that may be there (I haven't really noticed) is really just cosmetic and movement is fast.
Tags |
close me please, cry me a river, delete me, old thread, worstthreadever |
Thread Tools | |
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RISC machines execute multiple instructions in a single clock cycle these days - and so do CISC machines.
But it's even more exciting:
Modern x86 is something like RISC underneath. There is a sort of instruction translator running which reads the CISC instructions and converts them to a stream of RISC micro-ops (internal instructions). Several micro-ops are executed in parallel. Some micro-ops take multiple cycles each, or (on some x86s) half a cycle, but because they run in parallel the total time is lower, averaging to multiple micro-ops per cycle (typically about 2-3 depending on application, but memory access time is another major factor).
The N900's OMAP3 has a Cortex-A8 ARM core. Due to it's RISCy heritage, most instructions translate to one micro-ops internally but some translate to several. It can execute up to 2 micro-ops per clock cycle, depending on rules for dual issue. The ARM instruction set, although RISCy, is quite compact: It can do several things at once in the same instruction, and it's up clever compilers and code writers to take advantage of it.
The N900's OMAP3 also has a TI C64x DSP core, which uses a VLIW instruction set and executes up to 8 operations per cycle.
So you see, it is really not as simple as CISC vs RISC.
Generally, modern x86 performs very well because it's a highly optimised design. But it depends a lot on which chip family, as well as the clock speed. That's why the clock speed isn't as important in marketing any mode.
ARM performs very well while using much lower power than x86, and the DSP on the same chip can be used for number crunching (but it's not as open to use, unfortunately)
In general I expect the OMAP3 at 600MHz to perform better than any x86 clocked at 600MHz for most functions, but not necessarily everything.
(The x86s which squeeze a lot per cycle are usually run at higher clock speeds, so only older x86s or ones with less fancy designs are typically run at 600MHz).